From f3739ff05bcc9d17c37e462a5be029b1c03e2a1e Mon Sep 17 00:00:00 2001 From: Eugene Syromiatnikov Date: Aug 05 2024 17:06:15 +0000 Subject: Release. Intel CPU microcode update. 20240531 Signed-off-by: Eugene Syromiatnikov --- diff --git a/Changelog b/Changelog index cfcad8d..f427a5a 100644 --- a/Changelog +++ b/Changelog @@ -1,3 +1,213 @@ +2.1-43 05 Aug 2024, Eugene Syromiatnikov + Intel CPU microcode update. 20240531 + - Addition of 06-aa-04/0xe6 (MTL-H/U C0) microcode at revision 0x1c; + - Addition of 06-ba-08/0xe0 microcode (in intel-ucode/06-ba-02) at + revision 0x4121; + - Addition of 06-ba-08/0xe0 microcode (in intel-ucode/06-ba-03) at + revision 0x4121; + - Addition of 06-ba-02/0xe0 (RPL-H 6+8/P 6+8 J0) microcode (in + intel-ucode/06-ba-08) at revision 0x4121; + - Addition of 06-ba-03/0xe0 (RPL-U 2+8 Q0) microcode (in + intel-ucode/06-ba-08) at revision 0x4121; + - Addition of 06-ba-08/0xe0 microcode at revision 0x4121; + - Addition of 06-cf-01/0x87 (EMR-SP A0) microcode at revision + 0x21000230; + - Addition of 06-cf-02/0x87 (EMR-SP A1) microcode (in + intel-ucode/06-cf-01) at revision 0x21000230; + - Addition of 06-cf-01/0x87 (EMR-SP A0) microcode (in + intel-ucode/06-cf-02) at revision 0x21000230; + - Addition of 06-cf-02/0x87 (EMR-SP A1) microcode at revision + 0x21000230; + - Removal of 06-8f-04/0x10 microcode at revision 0x2c000290; + - Removal of 06-8f-04/0x87 (SPR-SP E0/S1) microcode at revision + 0x2b0004d0; + - Removal of 06-8f-05/0x10 (SPR-HBM B1) microcode (in + intel-ucode/06-8f-04) at revision 0x2c000290; + - Removal of 06-8f-05/0x87 (SPR-SP E2) microcode (in + intel-ucode/06-8f-04) at revision 0x2b0004d0; + - Removal of 06-8f-06/0x10 microcode (in intel-ucode/06-8f-04) at + revision 0x2c000290; + - Removal of 06-8f-06/0x87 (SPR-SP E3) microcode (in + intel-ucode/06-8f-04) at revision 0x2b0004d0; + - Removal of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in + intel-ucode/06-8f-04) at revision 0x2b0004d0; + - Removal of 06-8f-08/0x10 (SPR-HBM B3) microcode (in + intel-ucode/06-8f-04) at revision 0x2c000290; + - Removal of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in + intel-ucode/06-8f-04) at revision 0x2b0004d0; + - Update of 06-55-03/0x97 (SKX-SP B1) microcode from revision 0x1000181 + up to 0x1000191; + - Update of 06-55-06/0xbf (CLX-SP B0) microcode from revision 0x4003604 + up to 0x4003605; + - Update of 06-55-07/0xbf (CLX-SP/W/X B1/L1) microcode from revision + 0x5003604 up to 0x5003605; + - Update of 06-55-0b/0xbf (CPX-SP A1) microcode from revision 0x7002703 + up to 0x7002802; + - Update of 06-56-05/0x10 (BDX-NS A0/A1, HWL A1) microcode from revision + 0xe000014 up to 0xe000015; + - Update of 06-5f-01/0x01 (DNV B0) microcode from revision 0x38 up + to 0x3e; + - Update of 06-6a-06/0x87 (ICX-SP D0) microcode from revision 0xd0003b9 + up to 0xd0003d1; + - Update of 06-6c-01/0x10 (ICL-D B0) microcode from revision 0x1000268 + up to 0x1000290; + - Update of 06-7a-01/0x01 (GLK B0) microcode from revision 0x3e up + to 0x42; + - Update of 06-7a-08/0x01 (GLK-R R0) microcode from revision 0x22 up + to 0x24; + - Update of 06-7e-05/0x80 (ICL-U/Y D1) microcode from revision 0xc2 + up to 0xc4; + - Update of 06-8c-01/0x80 (TGL-UP3/UP4 B1) microcode from revision + 0xb4 up to 0xb6; + - Update of 06-8c-02/0xc2 (TGL-R C0) microcode from revision 0x34 up + to 0x36; + - Update of 06-8d-01/0xc2 (TGL-H R0) microcode from revision 0x4e up + to 0x50; + - Update of 06-8e-0c/0x94 (AML-Y 4+2 V0, CML-U 4+2 V0, WHL-U V0) + microcode from revision 0xf8 up to 0xfa; + - Update of 06-8f-04/0x10 microcode (in intel-ucode/06-8f-05) from + revision 0x2c000290 up to 0x2c000390; + - Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in + intel-ucode/06-8f-05) from revision 0x2b0004d0 up to 0x2b0005c0; + - Update of 06-8f-05/0x10 (SPR-HBM B1) microcode from revision + 0x2c000290 up to 0x2c000390; + - Update of 06-8f-05/0x87 (SPR-SP E2) microcode from revision 0x2b0004d0 + up to 0x2b0005c0; + - Update of 06-8f-06/0x10 microcode (in intel-ucode/06-8f-05) from + revision 0x2c000290 up to 0x2c000390; + - Update of 06-8f-06/0x87 (SPR-SP E3) microcode (in + intel-ucode/06-8f-05) from revision 0x2b0004d0 up to 0x2b0005c0; + - Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in + intel-ucode/06-8f-05) from revision 0x2b0004d0 up to 0x2b0005c0; + - Update of 06-8f-08/0x10 (SPR-HBM B3) microcode (in + intel-ucode/06-8f-05) from revision 0x2c000290 up to 0x2c000390; + - Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in + intel-ucode/06-8f-05) from revision 0x2b0004d0 up to 0x2b0005c0; + - Update of 06-8f-04/0x10 microcode (in intel-ucode/06-8f-06) from + revision 0x2c000290 up to 0x2c000390; + - Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in + intel-ucode/06-8f-06) from revision 0x2b0004d0 up to 0x2b0005c0; + - Update of 06-8f-05/0x10 (SPR-HBM B1) microcode (in + intel-ucode/06-8f-06) from revision 0x2c000290 up to 0x2c000390; + - Update of 06-8f-05/0x87 (SPR-SP E2) microcode (in + intel-ucode/06-8f-06) from revision 0x2b0004d0 up to 0x2b0005c0; + - Update of 06-8f-06/0x10 microcode from revision 0x2c000290 up to + 0x2c000390; + - Update of 06-8f-06/0x87 (SPR-SP E3) microcode from revision 0x2b0004d0 + up to 0x2b0005c0; + - Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in + intel-ucode/06-8f-06) from revision 0x2b0004d0 up to 0x2b0005c0; + - Update of 06-8f-08/0x10 (SPR-HBM B3) microcode (in + intel-ucode/06-8f-06) from revision 0x2c000290 up to 0x2c000390; + - Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in + intel-ucode/06-8f-06) from revision 0x2b0004d0 up to 0x2b0005c0; + - Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in + intel-ucode/06-8f-07) from revision 0x2b0004d0 up to 0x2b0005c0; + - Update of 06-8f-05/0x87 (SPR-SP E2) microcode (in + intel-ucode/06-8f-07) from revision 0x2b0004d0 up to 0x2b0005c0; + - Update of 06-8f-06/0x87 (SPR-SP E3) microcode (in + intel-ucode/06-8f-07) from revision 0x2b0004d0 up to 0x2b0005c0; + - Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode from revision + 0x2b0004d0 up to 0x2b0005c0; + - Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in + intel-ucode/06-8f-07) from revision 0x2b0004d0 up to 0x2b0005c0; + - Update of 06-8f-04/0x10 microcode (in intel-ucode/06-8f-08) from + revision 0x2c000290 up to 0x2c000390; + - Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in + intel-ucode/06-8f-08) from revision 0x2b0004d0 up to 0x2b0005c0; + - Update of 06-8f-05/0x10 (SPR-HBM B1) microcode (in + intel-ucode/06-8f-08) from revision 0x2c000290 up to 0x2c000390; + - Update of 06-8f-05/0x87 (SPR-SP E2) microcode (in + intel-ucode/06-8f-08) from revision 0x2b0004d0 up to 0x2b0005c0; + - Update of 06-8f-06/0x10 microcode (in intel-ucode/06-8f-08) from + revision 0x2c000290 up to 0x2c000390; + - Update of 06-8f-06/0x87 (SPR-SP E3) microcode (in + intel-ucode/06-8f-08) from revision 0x2b0004d0 up to 0x2b0005c0; + - Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in + intel-ucode/06-8f-08) from revision 0x2b0004d0 up to 0x2b0005c0; + - Update of 06-8f-08/0x10 (SPR-HBM B3) microcode from revision + 0x2c000290 up to 0x2c000390; + - Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode from revision + 0x2b0004d0 up to 0x2b0005c0; + - Update of 06-96-01/0x01 (EHL B1) microcode from revision 0x17 up + to 0x19; + - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode from revision + 0x32 up to 0x35; + - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in + intel-ucode/06-97-02) from revision 0x32 up to 0x35; + - Update of 06-bf-02/0x07 (ADL C0) microcode (in intel-ucode/06-97-02) + from revision 0x32 up to 0x35; + - Update of 06-bf-05/0x07 (ADL C0) microcode (in intel-ucode/06-97-02) + from revision 0x32 up to 0x35; + - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in + intel-ucode/06-97-05) from revision 0x32 up to 0x35; + - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode from revision 0x32 + up to 0x35; + - Update of 06-bf-02/0x07 (ADL C0) microcode (in intel-ucode/06-97-05) + from revision 0x32 up to 0x35; + - Update of 06-bf-05/0x07 (ADL C0) microcode (in intel-ucode/06-97-05) + from revision 0x32 up to 0x35; + - Update of 06-9a-03/0x80 (ADL-P 6+8/U 9W L0/R0) microcode from revision + 0x430 up to 0x433; + - Update of 06-9a-04/0x80 (ADL-P 2+8 R0) microcode (in + intel-ucode/06-9a-03) from revision 0x430 up to 0x433; + - Update of 06-9a-03/0x80 (ADL-P 6+8/U 9W L0/R0) microcode (in + intel-ucode/06-9a-04) from revision 0x430 up to 0x433; + - Update of 06-9a-04/0x80 (ADL-P 2+8 R0) microcode from revision 0x430 + up to 0x433; + - Update of 06-9a-04/0x40 (AZB A0) microcode from revision 0x5 up + to 0x7; + - Update of 06-9c-00/0x01 (JSL A0/A1) microcode from revision 0x24000024 + up to 0x24000026; + - Update of 06-9e-09/0x2a (KBL-G/H/S/X/Xeon E3 B0) microcode from + revision 0xf4 up to 0xf8; + - Update of 06-9e-0a/0x22 (CFL-H/S/Xeon E U0) microcode from revision + 0xf4 up to 0xf6; + - Update of 06-9e-0c/0x22 (CFL-H/S/Xeon E P0) microcode from revision + 0xf4 up to 0xf6; + - Update of 06-9e-0d/0x22 (CFL-H/S/Xeon E R0) microcode from revision + 0xfa up to 0xfc; + - Update of 06-a5-02/0x20 (CML-H R1) microcode from revision 0xf8 up + to 0xfa; + - Update of 06-a5-03/0x22 (CML-S 6+2 G1) microcode from revision 0xf8 + up to 0xfa; + - Update of 06-a5-05/0x22 (CML-S 10+2 Q0) microcode from revision 0xf8 + up to 0xfa; + - Update of 06-a6-00/0x80 (CML-U 6+2 A0) microcode from revision 0xf8 + up to 0xfa; + - Update of 06-a6-01/0x80 (CML-U 6+2 v2 K1) microcode from revision + 0xf8 up to 0xfa; + - Update of 06-a7-01/0x02 (RKL-S B0) microcode from revision 0x5d up + to 0x5e; + - Update of 06-b7-01/0x32 (RPL-S B0) microcode from revision 0x11d up + to 0x123; + - Update of 06-ba-02/0xe0 (RPL-H 6+8/P 6+8 J0) microcode from revision + 0x411c up to 0x4121; + - Update of 06-ba-03/0xe0 (RPL-U 2+8 Q0) microcode (in + intel-ucode/06-ba-02) from revision 0x411c up to 0x4121; + - Update of 06-ba-02/0xe0 (RPL-H 6+8/P 6+8 J0) microcode (in + intel-ucode/06-ba-03) from revision 0x411c up to 0x4121; + - Update of 06-ba-03/0xe0 (RPL-U 2+8 Q0) microcode from revision 0x411c + up to 0x4121; + - Update of 06-be-00/0x11 (ADL-N A0) microcode from revision 0x12 up + to 0x17; + - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in + intel-ucode/06-bf-02) from revision 0x32 up to 0x35; + - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in + intel-ucode/06-bf-02) from revision 0x32 up to 0x35; + - Update of 06-bf-02/0x07 (ADL C0) microcode from revision 0x32 up + to 0x35; + - Update of 06-bf-05/0x07 (ADL C0) microcode (in intel-ucode/06-bf-02) + from revision 0x32 up to 0x35; + - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in + intel-ucode/06-bf-05) from revision 0x32 up to 0x35; + - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in + intel-ucode/06-bf-05) from revision 0x32 up to 0x35; + - Update of 06-bf-02/0x07 (ADL C0) microcode (in intel-ucode/06-bf-05) + from revision 0x32 up to 0x35; + - Update of 06-bf-05/0x07 (ADL C0) microcode from revision 0x32 up + to 0x35. + 2.1-42 14 Nov 2023, Eugene Syromiatnikov Intel CPU microcode update. 20231114 - Update of 06-6a-06/0x87 (ICX-SP D0) microcode from revision 0xd0003a5 diff --git a/Makefile b/Makefile index c7dd7e6..2f26596 100644 --- a/Makefile +++ b/Makefile @@ -7,7 +7,7 @@ # as published by the Free Software Foundation; either version # 2 of the License, or (at your option) any later version. -MICROCODE_INTEL = microcode-20231114.tar.gz +MICROCODE_INTEL = microcode-20240531.tar.gz INS = install CC = gcc diff --git a/microcode-20231114.tar.gz b/microcode-20231114.tar.gz deleted file mode 100644 index 2d110d3..0000000 Binary files a/microcode-20231114.tar.gz and /dev/null differ diff --git a/microcode-20240531.tar.gz b/microcode-20240531.tar.gz new file mode 100644 index 0000000..1faa0b3 Binary files /dev/null and b/microcode-20240531.tar.gz differ diff --git a/microcode_ctl.spec b/microcode_ctl.spec index e8a9537..c19d77a 100644 --- a/microcode_ctl.spec +++ b/microcode_ctl.spec @@ -1,7 +1,7 @@ Summary: Tool to transform and deploy CPU microcode update for x86. Name: microcode_ctl Version: 2.1 -Release: 42 +Release: 43 Group: System Environment/Base License: GPLv2+ and Redistributable, no modification permitted URL: https://pagure.io/microcode_ctl/