From 83494d03cec6068746e24d83d9e9d0a49b73c83b Mon Sep 17 00:00:00 2001 From: Eugene Syromiatnikov Date: May 25 2023 16:56:39 +0000 Subject: Release. Intel CPU microcode update. 20230516 Signed-off-by: Eugene Syromiatnikov --- diff --git a/Changelog b/Changelog index 1241238..fea626e 100644 --- a/Changelog +++ b/Changelog @@ -1,3 +1,164 @@ +2.1-40 24 May 2023, Eugene Syromiatnikov + Intel CPU microcode update. 20230516 + - Addition of 06-9a-04/0x40 (AZB A0/R0) microcode at revision 0x4; + - Addition of 06-be-00/0x01 (ADL-N A0) microcode at revision 0x10; + - Update of 06-55-03/0x97 (SKX-SP B1) microcode from revision 0x1000161 + up to 0x1000171; + - Update of 06-55-04/0xb7 (SKX-D/SP/W/X H0/M0/M1/U0) microcode from + revision 0x2006e05 up to 0x2006f05; + - Update of 06-55-06/0xbf (CLX-SP B0) microcode from revision 0x4003303 + up to 0x4003501; + - Update of 06-55-07/0xbf (CLX-SP/W/X B1/L1) microcode from revision + 0x5003303 up to 0x5003501; + - Update of 06-55-0b/0xbf (CPX-SP A1) microcode from revision 0x7002503 + up to 0x7002601; + - Update of 06-6a-06/0x87 (ICX-SP D0) microcode from revision 0xd000389 + up to 0xd000390; + - Update of 06-6c-01/0x10 (ICL-D B0) microcode from revision 0x1000211 + up to 0x1000230; + - Update of 06-7e-05/0x80 (ICL-U/Y D1) microcode from revision 0xb8 + up to 0xba; + - Update of 06-8a-01/0x10 (LKF B2/B3) microcode from revision 0x32 up + to 0x33; + - Update of 06-8c-01/0x80 (TGL-UP3/UP4 B1) microcode from revision + 0xa6 up to 0xaa; + - Update of 06-8c-02/0xc2 (TGL-R C0) microcode from revision 0x28 up + to 0x2a; + - Update of 06-8d-01/0xc2 (TGL-H R0) microcode from revision 0x42 up + to 0x44; + - Update of 06-8e-09/0x10 (AML-Y 2+2 H0) microcode from revision 0xf0 + up to 0xf2; + - Update of 06-8e-09/0xc0 (KBL-U/U 2+3e/Y H0/J1) microcode from revision + 0xf0 up to 0xf2; + - Update of 06-8e-0a/0xc0 (CFL-U 4+3e D0, KBL-R Y0) microcode from + revision 0xf0 up to 0xf2; + - Update of 06-8e-0b/0xd0 (WHL-U W0) microcode from revision 0xf0 up + to 0xf2; + - Update of 06-8e-0c/0x94 (AML-Y 4+2 V0, CML-U 4+2 V0, WHL-U V0) + microcode from revision 0xf4 up to 0xf6; + - Update of 06-8f-04/0x10 microcode from revision 0x2c000170 up to + 0x2c0001d1; + - Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode from revision + 0x2b000181 up to 0x2b000461; + - Update of 06-8f-05/0x10 (SPR-HBM B1) microcode (in + intel-ucode/06-8f-04) from revision 0x2c000170 up to 0x2c0001d1; + - Update of 06-8f-05/0x87 (SPR-SP E2) microcode (in + intel-ucode/06-8f-04) from revision 0x2b000181 up to 0x2b000461; + - Update of 06-8f-06/0x10 (SPR-HBM B2) microcode (in + intel-ucode/06-8f-04) from revision 0x2c000170 up to 0x2c0001d1; + - Update of 06-8f-06/0x87 (SPR-SP E3) microcode (in + intel-ucode/06-8f-04) from revision 0x2b000181 up to 0x2b000461; + - Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in + intel-ucode/06-8f-04) from revision 0x2b000181 up to 0x2b000461; + - Update of 06-8f-08/0x10 (SPR-HBM B3) microcode (in + intel-ucode/06-8f-04) from revision 0x2c000170 up to 0x2c0001d1; + - Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in + intel-ucode/06-8f-04) from revision 0x2b000181 up to 0x2b000461; + - Update of 06-8f-04/0x10 microcode (in intel-ucode/06-8f-05) from + revision 0x2c000170 up to 0x2c0001d1; + - Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in + intel-ucode/06-8f-05) from revision 0x2b000181 up to 0x2b000461; + - Update of 06-8f-05/0x10 (SPR-HBM B1) microcode from revision + 0x2c000170 up to 0x2c0001d1; + - Update of 06-8f-05/0x87 (SPR-SP E2) microcode from revision 0x2b000181 + up to 0x2b000461; + - Update of 06-8f-06/0x10 (SPR-HBM B2) microcode (in + intel-ucode/06-8f-05) from revision 0x2c000170 up to 0x2c0001d1; + - Update of 06-8f-06/0x87 (SPR-SP E3) microcode (in + intel-ucode/06-8f-05) from revision 0x2b000181 up to 0x2b000461; + - Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in + intel-ucode/06-8f-05) from revision 0x2b000181 up to 0x2b000461; + - Update of 06-8f-08/0x10 (SPR-HBM B3) microcode (in + intel-ucode/06-8f-05) from revision 0x2c000170 up to 0x2c0001d1; + - Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in + intel-ucode/06-8f-05) from revision 0x2b000181 up to 0x2b000461; + - Update of 06-8f-04/0x10 microcode (in intel-ucode/06-8f-06) from + revision 0x2c000170 up to 0x2c0001d1; + - Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in + intel-ucode/06-8f-06) from revision 0x2b000181 up to 0x2b000461; + - Update of 06-8f-05/0x10 (SPR-HBM B1) microcode (in + intel-ucode/06-8f-06) from revision 0x2c000170 up to 0x2c0001d1; + - Update of 06-8f-05/0x87 (SPR-SP E2) microcode (in + intel-ucode/06-8f-06) from revision 0x2b000181 up to 0x2b000461; + - Update of 06-8f-06/0x10 (SPR-HBM B2) microcode from revision + 0x2c000170 up to 0x2c0001d1; + - Update of 06-8f-06/0x87 (SPR-SP E3) microcode from revision 0x2b000181 + up to 0x2b000461; + - Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in + intel-ucode/06-8f-06) from revision 0x2b000181 up to 0x2b000461; + - Update of 06-8f-08/0x10 (SPR-HBM B3) microcode (in + intel-ucode/06-8f-06) from revision 0x2c000170 up to 0x2c0001d1; + - Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in + intel-ucode/06-8f-06) from revision 0x2b000181 up to 0x2b000461; + - Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in + intel-ucode/06-8f-07) from revision 0x2b000181 up to 0x2b000461; + - Update of 06-8f-05/0x87 (SPR-SP E2) microcode (in + intel-ucode/06-8f-07) from revision 0x2b000181 up to 0x2b000461; + - Update of 06-8f-06/0x87 (SPR-SP E3) microcode (in + intel-ucode/06-8f-07) from revision 0x2b000181 up to 0x2b000461; + - Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode from revision + 0x2b000181 up to 0x2b000461; + - Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in + intel-ucode/06-8f-07) from revision 0x2b000181 up to 0x2b000461; + - Update of 06-8f-04/0x10 microcode (in intel-ucode/06-8f-08) from + revision 0x2c000170 up to 0x2c0001d1; + - Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in + intel-ucode/06-8f-08) from revision 0x2b000181 up to 0x2b000461; + - Update of 06-8f-05/0x10 (SPR-HBM B1) microcode (in + intel-ucode/06-8f-08) from revision 0x2c000170 up to 0x2c0001d1; + - Update of 06-8f-05/0x87 (SPR-SP E2) microcode (in + intel-ucode/06-8f-08) from revision 0x2b000181 up to 0x2b000461; + - Update of 06-8f-06/0x10 (SPR-HBM B2) microcode (in + intel-ucode/06-8f-08) from revision 0x2c000170 up to 0x2c0001d1; + - Update of 06-8f-06/0x87 (SPR-SP E3) microcode (in + intel-ucode/06-8f-08) from revision 0x2b000181 up to 0x2b000461; + - Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in + intel-ucode/06-8f-08) from revision 0x2b000181 up to 0x2b000461; + - Update of 06-8f-08/0x10 (SPR-HBM B3) microcode from revision + 0x2c000170 up to 0x2c0001d1; + - Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode from revision + 0x2b000181 up to 0x2b000461; + - Update of 06-9a-03/0x80 (ADL-P 6+8/U 9W L0/R0) microcode from revision + 0x429 up to 0x42a; + - Update of 06-9a-04/0x80 (ADL-P 2+8 R0) microcode (in + intel-ucode/06-9a-03) from revision 0x429 up to 0x42a; + - Update of 06-9a-03/0x80 (ADL-P 6+8/U 9W L0/R0) microcode (in + intel-ucode/06-9a-04) from revision 0x429 up to 0x42a; + - Update of 06-9a-04/0x80 (ADL-P 2+8 R0) microcode from revision 0x429 + up to 0x42a; + - Update of 06-9e-09/0x2a (KBL-G/H/S/X/Xeon E3 B0) microcode from + revision 0xf0 up to 0xf2; + - Update of 06-9e-0a/0x22 (CFL-H/S/Xeon E U0) microcode from revision + 0xf0 up to 0xf2; + - Update of 06-9e-0b/0x02 (CFL-E/H/S B0) microcode from revision 0xf0 + up to 0xf2; + - Update of 06-9e-0c/0x22 (CFL-H/S/Xeon E P0) microcode from revision + 0xf0 up to 0xf2; + - Update of 06-9e-0d/0x22 (CFL-H/S/Xeon E R0) microcode from revision + 0xf4 up to 0xf8; + - Update of 06-a5-02/0x20 (CML-H R1) microcode from revision 0xf4 up + to 0xf6; + - Update of 06-a5-03/0x22 (CML-S 6+2 G1) microcode from revision 0xf4 + up to 0xf6; + - Update of 06-a5-05/0x22 (CML-S 10+2 Q0) microcode from revision 0xf4 + up to 0xf6; + - Update of 06-a6-00/0x80 (CML-U 6+2 A0) microcode from revision 0xf4 + up to 0xf6; + - Update of 06-a6-01/0x80 (CML-U 6+2 v2 K1) microcode from revision + 0xf4 up to 0xf6; + - Update of 06-a7-01/0x02 (RKL-S B0) microcode from revision 0x57 up + to 0x58; + - Update of 06-b7-01/0x32 (RPL-S S0) microcode from revision 0x112 up + to 0x113; + - Update of 06-ba-02/0xc0 (RPL-H 6+8/P 6+8 J0) microcode from revision + 0x410e up to 0x4112; + - Update of 06-ba-03/0xc0 (RPL-U 2+8 Q0) microcode (in + intel-ucode/06-ba-02) from revision 0x410e up to 0x4112; + - Update of 06-ba-02/0xc0 (RPL-H 6+8/P 6+8 J0) microcode (in + intel-ucode/06-ba-03) from revision 0x410e up to 0x4112; + - Update of 06-ba-03/0xc0 (RPL-U 2+8 Q0) microcode from revision 0x410e + up to 0x4112. + 2.1-39 16 Feb 2023, Eugene Syromiatnikov Intel CPU microcode update. 20230214 - Addition of 06-8f-04/0x87 (SPR-SP E0/S1) microcode at revision diff --git a/Makefile b/Makefile index f08e9a8..e235de4 100644 --- a/Makefile +++ b/Makefile @@ -7,7 +7,7 @@ # as published by the Free Software Foundation; either version # 2 of the License, or (at your option) any later version. -MICROCODE_INTEL = microcode-20230214.tar.gz +MICROCODE_INTEL = microcode-20230516.tar.gz INS = install CC = gcc diff --git a/microcode-20230214.tar.gz b/microcode-20230214.tar.gz deleted file mode 100644 index 35a5698..0000000 Binary files a/microcode-20230214.tar.gz and /dev/null differ diff --git a/microcode-20230516.tar.gz b/microcode-20230516.tar.gz new file mode 100644 index 0000000..36cec82 Binary files /dev/null and b/microcode-20230516.tar.gz differ diff --git a/microcode_ctl.spec b/microcode_ctl.spec index 54034ba..68d1469 100644 --- a/microcode_ctl.spec +++ b/microcode_ctl.spec @@ -1,7 +1,7 @@ Summary: Tool to transform and deploy CPU microcode update for x86. Name: microcode_ctl Version: 2.1 -Release: 39 +Release: 40 Group: System Environment/Base License: GPLv2+ and Redistributable, no modification permitted URL: https://pagure.io/microcode_ctl/