From 7994443ca12c0a64d6fe87627c092c6b183e6ea1 Mon Sep 17 00:00:00 2001 From: Eugene Syromiatnikov Date: Jun 08 2021 17:21:29 +0000 Subject: Release. Intel CPU microcode update. 20210608 Signed-off-by: Eugene Syromiatnikov --- diff --git a/Changelog b/Changelog index 6f025a5..e24e946 100644 --- a/Changelog +++ b/Changelog @@ -1,3 +1,92 @@ +2.1-33 08 Jun 2021, Eugene Syromiatnikov + Intel CPU microcode update. 20210608 + - Addition of 06-55-05/0xb7 (CLX-SP A0) microcode at revision 0x3000010; + - Addition of 06-6a-05/0x87 (ICX-SP C0) microcode at revision 0xc0002f0; + - Addition of 06-6a-06/0x87 (ICX-SP D0) microcode at revision 0xd0002a0; + - Addition of 06-86-04/0x01 (SNR B0) microcode at revision 0xb00000f; + - Addition of 06-86-05/0x01 (SNR B1) microcode (in intel-ucode/06-86-04) + at revision 0xb00000f; + - Addition of 06-86-04/0x01 (SNR B0) microcode (in intel-ucode/06-86-05) + at revision 0xb00000f; + - Addition of 06-86-05/0x01 (SNR B1) microcode at revision 0xb00000f; + - Addition of 06-8c-01/0x80 (TGL-UP3/UP4 B1) microcode at revision 0x88; + - Addition of 06-8c-02/0xc2 (TGL-R C0) microcode at revision 0x16; + - Addition of 06-8d-01/0xc2 (TGL-H R0) microcode at revision 0x2c; + - Addition of 06-96-01/0x01 (EHL B1) microcode at revision 0x11; + - Addition of 06-9c-00/0x01 (JSL A0/A1) microcode at revision 0x1d; + - Addition of 06-a7-01/0x02 (RKL-S B0) microcode at revision 0x40; + - Update of 06-4f-01/0xef (BDX-E/EP/EX/ML B0/M0/R0) microcode (in + intel-ucode-with-caveats/06-4f-01) from revision 0xb000038 up to + 0xb00003e; + - Update of 06-3f-02/0x6f (HSX-E/EN/EP/EP 4S C0/C1/M1/R2) microcode + from revision 0x44 up to 0x46; + - Update of 06-3f-04/0x80 (HSX-EX E0) microcode from revision 0x16 up + to 0x19; + - Update of 06-4e-03/0xc0 (SKL-U/U 2+3e/Y D0/K1) microcode from revision + 0xe2 up to 0xea; + - Update of 06-55-03/0x97 (SKX-SP B1) microcode from revision 0x1000159 + up to 0x100015b; + - Update of 06-55-04/0xb7 (SKX-D/SP/W/X H0/M0/M1/U0) microcode from + revision 0x2006a0a up to 0x2006b06; + - Update of 06-55-06/0xbf (CLX-SP B0) microcode from revision 0x4003006 + up to 0x4003102; + - Update of 06-55-07/0xbf (CLX-SP/W/X B1/L1) microcode from revision + 0x5003006 up to 0x5003102; + - Update of 06-55-0b/0xbf (CPX-SP A1) microcode from revision 0x700001e + up to 0x7002302; + - Update of 06-56-03/0x10 (BDX-DE V2/V3) microcode from revision + 0x7000019 up to 0x700001b; + - Update of 06-56-04/0x10 (BDX-DE Y0) microcode from revision 0xf000017 + up to 0xf000019; + - Update of 06-56-05/0x10 (BDX-NS A0/A1, HWL A1) microcode from revision + 0xe00000f up to 0xe000012; + - Update of 06-5c-09/0x03 (APL D0) microcode from revision 0x40 up + to 0x44; + - Update of 06-5c-0a/0x03 (APL B1/F1) microcode from revision 0x1e up + to 0x20; + - Update of 06-5e-03/0x36 (SKL-H/S/Xeon E3 N0/R0/S0) microcode from + revision 0xe2 up to 0xea; + - Update of 06-5f-01/0x01 (DNV B0) microcode from revision 0x2e up + to 0x34; + - Update of 06-7a-01/0x01 (GLK B0) microcode from revision 0x34 up + to 0x36; + - Update of 06-7a-08/0x01 (GLK-R R0) microcode from revision 0x18 up + to 0x1a; + - Update of 06-7e-05/0x80 (ICL-U/Y D1) microcode from revision 0xa0 + up to 0xa6; + - Update of 06-8a-01/0x10 (LKF B2/B3) microcode from revision 0x28 up + to 0x2a; + - Update of 06-8e-09/0x10 (AML-Y 2+2 H0) microcode from revision 0xde + up to 0xea; + - Update of 06-8e-09/0xc0 (KBL-U/U 2+3e/Y H0/J1) microcode from revision + 0xde up to 0xea; + - Update of 06-8e-0a/0xc0 (CFL-U 4+3e D0, KBL-R Y0) microcode from + revision 0xe0 up to 0xea; + - Update of 06-8e-0b/0xd0 (WHL-U W0) microcode from revision 0xde up + to 0xea; + - Update of 06-8e-0c/0x94 (AML-Y 4+2 V0, CML-U 4+2 V0, WHL-U V0) + microcode from revision 0xde up to 0xea; + - Update of 06-9e-09/0x2a (KBL-G/H/S/X/Xeon E3 B0) microcode from + revision 0xde up to 0xea; + - Update of 06-9e-0a/0x22 (CFL-H/S/Xeon E U0) microcode from revision + 0xde up to 0xea; + - Update of 06-9e-0b/0x02 (CFL-E/H/S B0) microcode from revision 0xde + up to 0xea; + - Update of 06-9e-0c/0x22 (CFL-H/S/Xeon E P0) microcode from revision + 0xde up to 0xea; + - Update of 06-9e-0d/0x22 (CFL-H/S/Xeon E R0) microcode from revision + 0xde up to 0xea; + - Update of 06-a5-02/0x20 (CML-H R1) microcode from revision 0xe0 up + to 0xea; + - Update of 06-a5-03/0x22 (CML-S 6+2 G1) microcode from revision 0xe0 + up to 0xea; + - Update of 06-a5-05/0x22 (CML-S 10+2 Q0) microcode from revision 0xe0 + up to 0xec; + - Update of 06-a6-00/0x80 (CML-U 6+2 A0) microcode from revision 0xe0 + up to 0xe8; + - Update of 06-a6-01/0x80 (CML-U 6+2 v2 K1) microcode from revision + 0xe0 up to 0xea. + 2.1-32 17 Feb 2021, Eugene Syromiatnikov Intel CPU microcode update. 20210216 - Update of 06-55-04/0xb7 (SKX-D/SP/W/X H0/M0/M1/U0) microcode from diff --git a/Makefile b/Makefile index b2bc39a..0b86a28 100644 --- a/Makefile +++ b/Makefile @@ -7,7 +7,7 @@ # as published by the Free Software Foundation; either version # 2 of the License, or (at your option) any later version. -MICROCODE_INTEL = microcode-20210216.tar.gz +MICROCODE_INTEL = microcode-20210608.tar.gz INS = install CC = gcc diff --git a/microcode-20210216.tar.gz b/microcode-20210216.tar.gz deleted file mode 100644 index c28360d..0000000 Binary files a/microcode-20210216.tar.gz and /dev/null differ diff --git a/microcode-20210608.tar.gz b/microcode-20210608.tar.gz new file mode 100644 index 0000000..0d66a7e Binary files /dev/null and b/microcode-20210608.tar.gz differ diff --git a/microcode_ctl.spec b/microcode_ctl.spec index ac19266..2a6a985 100644 --- a/microcode_ctl.spec +++ b/microcode_ctl.spec @@ -1,7 +1,7 @@ Summary: Tool to transform and deploy CPU microcode update for x86. Name: microcode_ctl Version: 2.1 -Release: 32 +Release: 33 Group: System Environment/Base License: GPLv2+ and Redistributable, no modification permitted URL: https://pagure.io/microcode_ctl/