[X86] AMD Zen 3: 32/64 -bit GPR register moves are zero-cycle
    
    I've verified this with llvm-exegesis.
    This is not limited to zero registers.
    
    Refs:
    AMD SOG 19h, 2.9.4 Zero Cycle Move
    The processor is able to execute certain register to register
    mov operations with zero cycle delay.
    
    Agner,
    22.13 Instructions with no latency
    Register-to-register move instructions are resolved at
    the register rename stage without using any execution units.
    These instructions have zero latency. It is possible to do six such
    register renamings per clock cycle, and it is even possible to
    rename the same register multiple times in one clock cycle.