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@@ -37,6 +37,14 @@
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status |= attempt_rw(rwfd, buf, SIZE, 0, READ, -EFAULT);
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res = munmap(buf, page_size); assert(res == 0);
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+
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+ /* As of June 28th, 2022, the RISC-V spec Volume 2 Section 4.3
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+ * version "20211203 Privileged Architecture v1.12, Ratified"
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+ * reserves the usage of the PTE permission bit combination of
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+ * "write+!read", so the next test leads to undefined behavior
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+ * and should be disabled. */
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+ #ifndef __riscv
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+
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buf = mmap(0, page_size, PROT_WRITE, MAP_SHARED, rwfd, 0);
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assert(buf != (char *)-1);
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@@ -48,6 +56,8 @@
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status |= attempt_rw(rwfd, buf, SIZE, 0, READ, SIZE);
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status |= attempt_rw(rwfd, buf, SIZE, 0, WRITE, res);
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+ #endif
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+
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return status;
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}
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xctan
commented 2 years ago
As of June 28th, 2022, the RISC-V spec1 reserves the PTE permission bit
combination of "write+!read", and the kernel would have incoherent behavior in
the last test case of "harness/cases/5.t". Since it leads to undefined behavior,
until further spec update, this test case should be disabled for RISC-V.
A patch to disallow such permission in mmap() can be found here2.