7adf255 Add endian detection (LE) and bit width detection (32/64) for RISC-V

1 file Authored by Icenowy Zheng 6 years ago, Committed by jmoyer 6 years ago,
1 file changed. 2 lines added. 1 lines removed.
    Add endian detection (LE) and bit width detection (32/64) for RISC-V
    
    On the RISC-V architecture, the toolchain should define __riscv macro
    and a __riscv_xlen macro, which indicates the length of registers (also
    the length of pointers and the length of the C language long type).
    
    Use them to detect the RISC-V architecture, and set them in the
    LE32/LE64 codepath.
    
    Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
    Signed-off-by: Jeff Moyer <jmoyer@redhat.com>
    
        
file modified
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