OvmfPkg/PlatformPei: set 32-bit UC area at PciBase / PciExBarBase (pc/q35)
    
    (This is a replacement for commit 39b9a5ffe661 ("OvmfPkg/PlatformPei: fix
    MTRR for low-RAM sizes that have many bits clear", 2019-05-16).)
    
    Reintroduce the same logic as seen in commit 39b9a5ffe661 for the pc
    (i440fx) board type.
    
    For q35, the same approach doesn't work any longer, given that (a) we'd
    like to keep the PCIEXBAR in the platform DSC a fixed-at-build PCD, and
    (b) QEMU expects the PCIEXBAR to reside at a lower address than the 32-bit
    PCI MMIO aperture.
    
    Therefore, introduce a helper function for determining the 32-bit
    "uncacheable" (MMIO) area base address:
    
    - On q35, this function behaves statically. Furthermore, the MTRR setup
      exploits that the range [0xB000_0000, 0xFFFF_FFFF] can be marked UC with
      just two variable MTRRs (one at 0xB000_0000 (size 256MB), another at
      0xC000_0000 (size 1GB)).
    
    - On pc (i440fx), the function behaves dynamically, implementing the same
      logic as commit 39b9a5ffe661 did. The PciBase value is adjusted to the
      value calculated, similarly to commit 39b9a5ffe661. A further
      simplification is that we show that the UC32 area size truncation to a
      whole power of two automatically guarantees a >=2GB base address.
    
    Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
    Cc: Gerd Hoffmann <kraxel@redhat.com>
    Cc: Jordan Justen <jordan.l.justen@intel.com>
    Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1859
    Signed-off-by: Laszlo Ersek <lersek@redhat.com>
    Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com>
    Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>