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d99dcd5
GL simulation fixes
Authored and Committed by Marwan Abbas
2 years ago
raw
patch
tree
parent
8 files changed.
30 lines added
.
60 lines removed
.
verilog/dv/io_ports/io_ports.c
file modified
+0
-1
verilog/dv/io_ports/io_ports_tb.v
file modified
+3
-7
verilog/dv/la_test1/la_test1.c
file modified
+1
-1
verilog/dv/la_test1/la_test1_tb.v
file modified
+0
-5
verilog/dv/la_test2/la_test2_tb.v
file modified
+0
-4
verilog/dv/mprj_stimulus/mprj_stimulus.c
file modified
+5
-11
verilog/dv/mprj_stimulus/mprj_stimulus_tb.v
file modified
+18
-24
verilog/dv/wb_port/wb_port_tb.v
file modified
+3
-7
GL simulation fixes
verilog/dv/io_ports/io_ports.c
file modified
+0
-1
verilog/dv/io_ports/io_ports_tb.v
file modified
+3
-7
verilog/dv/la_test1/la_test1.c
file modified
+1
-1
verilog/dv/la_test1/la_test1_tb.v
file modified
+0
-5
verilog/dv/la_test2/la_test2_tb.v
file modified
+0
-4
verilog/dv/mprj_stimulus/mprj_stimulus.c
file modified
+5
-11
verilog/dv/mprj_stimulus/mprj_stimulus_tb.v
file modified
+18
-24
verilog/dv/wb_port/wb_port_tb.v
file modified
+3
-7