Hi there,
@aekoroglu, @oidoming, and myself recently joined the Hyperscale SIG on behalf of Intel. We'll be working on package maintenance of optimization work, but also supporting SIG-wide CI/CD automation. Towards both of those goals, Intel wants to make current (Ice Lake) and eventually next-gen hardware available to the SIG for building and testing packages. This ticket is to start that conversation, discuss that process, learn what requirements there are, and work through the process of adding new hardware. @bstinson also asked to be CC'd on this process.
Ideally, we'd like to plug in hardware we (Intel) host through some sort of openinfra framework. We were told that the hardware that currently supports the Hyperscale SIG is all at a RHEL-hosted datacenter. What kind of flexibility is there on adding outside-hosted hardware into the build environment?
If that flexibility is currently limited, we'd like to push for such capabilities going forward and are happy to work through that process. If this is supported already, what are the next steps toward such an integration? Right now we're happy to start small -- say, 1-3 additional Ice Lake machines.
Cheers and thanks for your time, Kevin
Metadata Update from @arrfab: - Issue tagged with: need-more-info
Hey @arrfab -- I saw this was tagged with need-more-info. Is there specific information you would need from us that I can gather?
need-more-info
it was tagged with need-more-info as it seems there was some discussion with Brian so we'll wait for more info to see what was discussed already outside of this ticket. @bstinson : feel free to ping me to discuss it as normally we don't allow remote builders for koji so would like some context around this request (missing context and info)
This issue has kind of stalled, so I'm hoping to restart it. @bstinson and I had been conversing via email, but it's been a few weeks since his last reply.
To reiterate our goals, we'd like to make hardware available for the SIG (and CentOS Stream in general) to run and test on. Further, some software optimization work we intend to work in the Hyperscale SIG will have functionality that we'd need IA hardware to either build or test the optimization feature, or both.
We want to understand the current setup and limitations, and discuss how we might reach this goal. Ideally, we'd host the hardware ourselves and plug it in through some kind of open-hardware interface.
Cheers, Kevin
@arrfab @bstinson What's the correct next step to resume this conversation?
As @bstinson said to me, he wanted to drive the discussion so I'll let him see with you and explain the various constraints
@bstinson -- what's the best way to resume this topic? This is still a priority for Intel.
Revisiting tickets and still wondering about this one : can it be closed if nothing will happen ?
Metadata Update from @arrfab: - Issue priority set to: Waiting on External (was: Needs Review)
@arrfab -- We were never able to gain traction on this topic. The last we heard was that similar requests had been made by others, and there was interest in finding a solution, but this capability was still not yet possible at this time.
As a result, I believe this issue can be closed, but Intel is still interested in pursuing this if the capability is ever developed.
Metadata Update from @arrfab: - Issue close_status updated to: Insufficient Data - Issue status updated to: Closed (was: Open)
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