Don't decode powerpc insns with invalid fields
    
    Certain insns have restrictions on fields.  For example, the insn
    mentioned in the PR, lqarx, must specify an even general purpose
    register as its destination and that register cannot appear in
    either of the base or index reg fields.  This holds even when the RA0
    field is 0 (meaning a zero rather than r0).
    
    	PR 21124
    	* ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
    	(extract_raq, extract_ras, extract_rbx): New functions.
    	(powerpc_operands): Use opposite corresponding insert function.
    	(Q_MASK): Define.
    	(powerpc_opcodes): Apply Q_MASK to all quad insns with even
    	register restriction.